Fabrication and characterisation of multi-level lateral nano-devices

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DOIResolve DOI: http://doi.org/10.1016/0039-6028(94)90971-7
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TypeArticle
Journal titleSurface Science
ISSN0039-6028
Volume305
Issue1-Mar
Pages648653; # of pages: 6
SubjectElectron transitions; Gates (transistor); Semiconducting aluminum compounds; Semiconducting gallium arsenide; Semiconductor device structures; Semiconductor quantum wells; Surfaces; Artificial impurity; Multilevel lateral nano-devices; Quantum dot; Quantum interference effects; Ring geometry; Semiconducting aluminum gallium arsenide; Surface gate patterns; Semiconductor device manufacture
AbstractThe design of surface gate patterns, used to define nanostructurcs in AlGaAs GaAs heterostructures, is greatly enhanced by the possibility of establishing electrical contact to, and independently biasing, a 100 nm wide isolated gate. We describe the fabrication of a multi-level metallisation architecture which can be used to contact a nanoscale central gate and monitor the transition from a quantum dot to ring geometry. We employ geometry induced quantum interference effects as a novel low temperature characterisation tool and report experiments in which the central electrode acts as an artificial impurity. © 1994.
Publication date
LanguageEnglish
AffiliationNational Research Council Canada (NRC-CNRC); NRC Institute for Microstructural Sciences
Peer reviewedYes
NPARC number21274634
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Record identifier1af138e6-6c21-4920-9cd5-05e5a0adcd1f
Record created2015-03-18
Record modified2016-05-09
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