Silicon photonic integration platform-Have we found the sweet spot?

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DOIResolve DOI: http://doi.org/10.1109/JSTQE.2014.2299634
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TypeArticle
Journal titleIEEE Journal on Selected Topics in Quantum Electronics
ISSN1077-260X
Volume20
Issue4
Article number6709757
AbstractThe current trend in silicon photonics towards higher levels of integration as well as the model of using CMOS foundries for fabrication are leading to a need for standardization of substrate parameters and fabrication processes. In particular, for several established research and development foundries that grant general access, silicon-on-insulator wafers with a silicon thickness of 220 nm have become the standard substrate for which devices and circuits have to be designed. In this study we investigate the role of silicon device layer thickness in design optimization of various components that need to be integrated in a typical optical transceiver, including both passive ones for routing, wavelength selection, and light coupling as well as active ones such as monolithic modulators and on-chip lasers produced by hybrid integration. We find that in all devices considered there is an advantage in using a silicon thickness larger than 220 nm, either for improved performance or for simplified fabrication processes and relaxed tolerances. © 2014 IEEE.
Publication date
LanguageEnglish
AffiliationNational Research Council Canada (NRC-CNRC); Information and Communication Technologies (ICT-TIC)
Peer reviewedYes
NPARC number21272184
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Record identifier363762ca-f495-40d1-8a99-aaa6f3b1848b
Record created2014-07-23
Record modified2016-05-09
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