Systematic methods to evaluate fault-tolerant behavior of nanoscale circuits

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DOIResolve DOI: http://doi.org/10.1166/asl.2011.1973
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TypeArticle
Journal titleAdvanced Science Letters
ISSN1936-6612
Volume4
Issue11-Dec
Pages34963507; # of pages: 12
AbstractThis paper focuses on the investigation of efficient methods to evaluate circuit fault-tolerance. We propose a fault-tolerance evaluation method based on the Belief Propagation (BP) algorithm. Compared with existing approaches, our algorithm is more efficient in terms of memory requirements and CPU time. The algorithm can easily run on multiple CPUs to achieve parallel processing, and thus further reducing memory cost and processing time. The significance of this research is that the proposed algorithm can be used for developing computer-aided nanoscale simulation tools to systemically evaluate circuit fault-tolerant behavior. This knowledge, in turn, can help build more robust nanocircuits. © 2011 American Scientific Publishers.
Publication date
LanguageEnglish
AffiliationNational Research Council Canada (NRC-CNRC); National Institute for Nanotechnology (NINT-INNT)
Peer reviewedYes
NPARC number21271583
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Record identifier703e8c50-f680-42ba-b695-c099a9095479
Record created2014-03-24
Record modified2016-05-09
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