Good 150oC Retention and Fast Erase Characteristics in Charge-Trap-Engineered Memory having a Scaled Si3N4 Layer

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DOIResolve DOI: http://doi.org/10.1109/IEDM.2008.4796829
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TypeArticle
Journal titleElectron Devices Meeting, 2008. IEDM 2008. IEEE International
Pages14; # of pages: 4
AbstractWe report a new charge-trap-engineered flash non-volatile memory that has combined 5 nm Si3N4 and 0.9 nm EOT HfON trapping layers, within double-barrier and double-tunnel layers. At 150degC under a 100 mus and plusmn16 V P/E, this device showed good device integrity of a 5.6 V initial DeltaVth window and 3.8 V 10-year extrapolated retention window. These data are better than the 3.3 V initial DeltaVth and 1.7 V 10-year data for a similar structure not having the extra HfON layer.
Publication date
LanguageEnglish
AffiliationNational Research Council Canada; NRC Institute for Microstructural Sciences
Peer reviewedNo
NPARC number16891228
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Record identifier7e66e906-0f04-40f3-92fc-04c3d1b5522d
Record created2011-03-26
Record modified2016-05-09
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