Layout versus schematic in multilayered printed electronics designs

AuthorSearch for:
TypeArticle
ConferenceLOPEC 2017, 28-30 March, 2017, Munich, Germany
AbstractA critical step in the production of integrated circuits (ICs) is layout versus schematic (LVS). The LVS process ensures that the interconnection of physical layers in the fabrication process of an IC matches the desired schematic. As circuit complexity increases, as is increasingly becoming the case for printed electronics designs, the need for LVS becomes paramount. Design errors in layout explode the cost of a project by wasting time and materials on a design bound to fail. Described herein are the extraction rules which allow LVS to be performed on multilayer printed electronics design with organic field effect transistors using standard IC design software, advancing the progress towards a complete integrated development environment for printed electronics.
Publication date
LanguageEnglish
AffiliationNational Research Council Canada; Information and Communication Technologies
Peer reviewedNo
NPARC number23002550
Export citationExport as RIS
Report a correctionReport a correction
Record identifierc5134719-c0de-404f-9738-220b8c6360bd
Record created2017-11-29
Record modified2017-11-29
Bookmark and share
  • Share this page with Facebook (Opens in a new window)
  • Share this page with Twitter (Opens in a new window)
  • Share this page with Google+ (Opens in a new window)
  • Share this page with Delicious (Opens in a new window)
Date modified: